基于veriloghdl的异步FIFO毕业论文.docVIP

PAGE   PAGE \* MERGEFORMAT 4 (此文档为word格式，下载后您可任意编辑修改！) 题 目 基于verilog and accomplish asynchronous FIFO based on Verilog HDL Abstract In modern IC design, particularly in the communications module and peripheral chip design, multiple clock domains of the inevitable. When data passes from one clock domain to another domain, and the target clock domains are not associated with the source clock domain, these domains are not related movements, thus eliminating the possibility of simultaneous operation and allows the system to enter the sub-repeat steady-state, causing disorder on the system clock timing. In order to effectively solve this problem, we use a asynchronous FIFO (FIFO) memory to achieve. This paper proposes a novel asynchronous FIFO design, which compared reading and writing through the first address and generate an asynchronous combination of quadrant detection empty full flag, then asynchronous empty full flag synchronized to the corresponding clock domain. The simulation results that the method is stable and effective. Key Words: asynchronous; FIFO; metastable state; Gray code; tie knots France 目 录  TOC \o 1-4 \h \z \u 1 引言  PAGEREF _Toc246848770 \h 1 1.1 FIFO研究意义  PAGEREF _Toc246848771 \h 1 1.2 生产需求状况  PAGEREF _Toc246848772 \h 1 1.3 存储器外发展状况  PAGEREF _Toc246848773 \h 2 1.4 FIFO设计技术简介  PAGEREF _Toc246848774 \h 4 1.4.1 基于信元的FIFO设计方法  PAGEREF _Toc246848775 \h 4 1.4.2 基于SRAMDRAM的大容量FIFO的设计与实现  PAGEREF _Toc246848776 \h 4 1.5 异步FIFO设计中存在的问题及解决办法  PAGEREF _Toc246848777 \h 5 1.5.1 亚稳态  PAGEREF _Toc246848778 \h 5 1.5.2 空满指针的解决方法  PAGEREF _Toc246848779 \h 6 1.6 论文主要内容  PAGEREF _Toc246848780 \h 6 2 异步FIFO工作原理简介  PAGEREF _Toc246848781 \h 7 2.1 关于异步信号  PAGEREF _Toc246848782 \h 7 2.2 异步FIFO芯片简介  PAGEREF _Toc246848783 \h 8 2.3 FIFO的一些重要参数  PAGEREF _Toc246848784 \h 9 2.4 异步FIFO设计的难点  PAGEREF _Toc246848785 \h 10 2.4.1 异步FIFO设计难点概述  PAGEREF _Toc246848786 \h 10 2.4.1.1 解决FIFO的满空技术方法概述和特点  PAGEREF _Toc246