第6章VHDL的基本描述语句.pptVIP

第6章 VHDL的基本描述语句;;6.1 顺序语句; IF 条件 THEN 语句 ； ELSIF 条件 THEN 语句 ； ELSIF 条件 THEN 语句 ； …… ELSE 语句 ； END IF;;LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY ddf IS PORT (CLK : IN STD_LOGIC ; D : IN STD_LOGIC ; Q, QD: OUT STD_LOGIC ); END ddf; ARCHITECTURE ex OF ddf IS BEGIN ;PROCESS (CLK) BEGIN IF (CLKEVENT) AND (CLK = 1‘) THEN Q = D; QD= not D; END IF; END PROCESS ; END ARCHITECTURE ex ;; 【例】用VHDL设计一家用告警系统的控制逻辑，它有来自传感器的三个输入信号smoke、door、water和准备传输到告警设备的三个输出触发信号fire_alarm、burg_alarm、water_alarm以及使能信号en和alarm_en。;PROCESS(smoke,door,water,en,alarm_en) BEGIN  IF ((smoke= ‘1’) AND (en= ‘0’)) THEN  fire_alarm = ‘1’;  ELSE  fire_alarm = ‘0’;  END IF;;; PORT(… z1 , z2 , z3 , z4 : out std_logic); … SIGNAL value : INTEGER RANGE 0 TO 15; CASE value IS WHEN 0 = z1 = ‘1’ ; - - value=0时 WHEN 1 | 3 = z2 = ‘0’ ; - - value=1或3时 WHEN 4 TO 7 | 2 = z3 = ‘1’ ; - - value=4、5、6、7或2时 WHEN OTHERS = z4 = ‘1’ ; - - value=8~15时 END CASE; SIGNAL value : INTEGER RANGE 0 TO 15; SIGNAL out1 : STD_LOGIC ; ... CASE value IS -- 缺少以WHEN引导的条件句 END CASE； ... CASE value IS WHEN 0 = out1= 1 ; -- value2～15的值未包括进去 WHEN 1 = out1= 0 ; END CASE ... CASE value IS WHEN 0 TO 10 = out1= 1;-- 选择值中5～10的值有重叠 WHEN 5 TO 15 = out1= 0; END CASE;; 【例】（3-8译码器） library ieee; use ieee.std_logic_1164.all; entity decode38 is port(a,b,c,G1,G2,G2B: in std_logic; y: out std_logic_vector(7 downto 0)); end entity decode38; architecture ex of decode38 is signal indata: std_logic_vector(2 downto 0); begin indata= c b a; process(indata,G1,G2,G2B) begin if(G1 = 1and G2 = 0 and G2B = 0) then ; case indata is when 000 = y = when 001 = y = whe