EDA设计参考程序完整版,合计31题剖析.doc

1、设计一个带计数使能、异步复位、带进位输出的减1三位二进制计数器，结果由共阴极七段数码管显示。 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(clk,en,clr:in std_logic; ledout:out std_logic_vector(6 downto 0); co:out std_logic); end counter; architecture a of counter is signal cnt:std_logic_vector(2 downto 0); signal hex:std_logic_vector(2 downto 0); begin process(clk) begin if clr=1then cnt=(others=0); elsif(clkevent and clk=1)then if en=1then if cnt=000then cnt=111; co=1; else cnt=cnt-1; co=0; end if; end if; end if; end process; hex=cnt(2 downto 0);