基于门节点分级选择的CMOL电路单元快速容错映射.pdf

第 29 卷 第 1 期 计算机辅助设计与图形学学报 Vol. 29 No.1 2017 年 1 月 Journal of Computer-Aided Design Computer Graphics Jan. 2017 基于门节点分级选择的CMOL 电路单元快速容错映射 * 汪纪波, 夏银水, 储著飞, 王伦耀 (宁波大学信息科学与工程学院 宁波 315211) (xiayinshui@nbu.edu.cn) : 针对存在缺陷 CMOL 电路的单元容错映射问题, 提出了一种分级选择电路门节点的容错映射方法. 首先通 过拓扑排序求出电路门的逻辑级 ; 然后采用级间隔的方式进行选择, 并对有缺陷连接的门节点进行惩罚 , 提高其被 选择配置的概率 . 实验结果表明, 与已有算法相比, 该方法平均选择配置的门节点总数明显减少 , 在纳米二极管常开 缺陷密度为 40% 、牺牲 0.18%线长的情况下, CPU 平均运行时间减少了 30.68%. ：CMOL 电路; 容错映射 ; 逻辑级 ：TP391.41 Fast Cells Defect-Tolerant Mapping Based on Gate Node Interval Selection in CMOL Circuits * Wang Jibo, Xia Yinshui , Chu Zhufei, and Wang Lunyao (School of Information Science and Engineering, Ningbo University, Ningbo 315211) Abstract: For the problem of cells defect-tolerant mapping in defect existed CMOL circuits, this paper proposes a defect-tolerant mapping method based on gate node interval selection. The logic circuit is topologically sorted to calculate the gate logic level, then interval gate nodes with defective connects are punished to improve the se- lected probability to be reallocated. The experiment results indicated that compared with the published algorithms, the proposed method shows that 30.68% of CPU runtime is reduced traded with 0.18% increase of wire length when the struck-open defect rate of nano-devices is up to 40%. Key words: CMOL circuit; defect-tolerant mapping; logic level CMOL (Cmos/nanowire/MOLecular hybrid, CMOS [2]. CMOL)[1] CMOS , , , 103 ~ 101 , CMOS CMOS , 9 7 [3] 10 ~ 10 . . ,