基于PFGA的数字跑表(国外英文资料).docVIP

基于PFGA的数字跑表 Based on the FPGA digital stopwatch College: college of electrical and electrical Name: CAI jinhua Student number:Class: 08 (27) Date: June 28, 2011 directory The main content of the instance is 3 Objective: 4 The first design method of the Verilog HDL language is 4 Complete a digital stop-watch design. 4 Experiment principle: 4 Program code and analysis 5 Five, the experiment step 9 5.1 create a new folder, 9 Build project 10 Compile and run program 13 5.4 import waveform 14 5.5 shows waveform 17 The 5.6 waveform runs after the result 18 5.5.7 is allocated 20 The 5.8-pin allocation completes figure 21 6, design tips 22 Reference 22 First, the main content of the experiment A written by Verilog HDL language are hundreds of minutes and seconds, digital stopwatch timing function, can realize accurate to of a second timer within an hour. The display of the digital stopwatch can be done by writing a digital tube display program. The design of counting and carry is implemented, and a specific purpose module is implemented through the design of several always modules. Objective: A preliminary approach to the design of the Verilog HDL language Complete a digital stop-watch design. The principle of experiment: The list starts with the lowest 100 minute counter, counting the system clock. Counting to 100 seconds counter is just a count of the clock count of a hundredth of a second counter. Counting to 60, the counter is carried to the counter, and the counter is counted as the clock by the carry bit of the second counter. The digital stopwatch is a clever use of the carry bit as a clock to reduce the number of digits. If you use the system clock as the counter clock, the second counter will be a 6,000-plus counter, which will be a 3600000 decimal counter. This will greatly waste the logical resources of the FPGA. Using the carry bit as a counting clock, you only need a 100 decimal counter and two 60-plus counters. In the actual design, the counters are