硬件描述措辞.docVIP

硬件描述语言 /xiaoyuan/beijing/707865.html Verilog HDL偏重于硬件一些，底层综合做得非常好； VHDL的逻辑综合比Verilog HDL要出色一些； Verilog HDL着重强调集成电路的综合，而VHDL强调于组合逻辑的综合。 module d_flop(d,q,clr,clk,enable); output q; input d,clr,clk,enable; reg q; always@(clr) if(!clr) q=0; else q=q; always@(posedge clk) if(enable) q=d; endmodule module two_fen(data_out,clr,clk); input clr,clk; output data_out; wire enableb; assign enableb=1; d_flop U1(~data_out,data_out,clr,clk,enableb); endmodule `timescale 1ns/1ns module two_fen_tb; reg clk,clr; initial begin clr=0; #5 clr=1; #3000; end initial begin repeat(1000) begin clk=0; #10 clk=1; #10 clk=0; end end two_fen U(.data_out(data_out), .clk(clk), .clr(clr)); endmodule `timescale 1ns/1ns module ten_counter_tb; reg clk,clr,enable; initial begin clr=0; #5 clr=1; #3000; end initial begin repeat(1000) begin clk=0; #10 clk=1; #10 clk=0; end end initial begin enable=1; #8 enable=0; #5 enable=1; #3000; end ten_counter U( .clk(clk), .clr(clr), .enable(enable), .Q(Q)); endmodule module ten_counter(clk,clr,enable,Q); input clk,clr,enable; output [3:0] Q; wire w1,w2,w3,clrb; wire[3:0]D; wire [3:0] Q; xor X1(D[1],Q[0],Q[1]), X2(D[2],w1,Q[2]), X3(D[3],w2,Q[3]); and A1(w1,Q[0],Q[1]), A2(w2,Q[2],w1), A3(clrb,w3,clr); not N1(D[0],Q[0]); nand NA(w3,Q[1],Q[3]); d_flop U1(D[0],Q[0],clrb,clk,enable), U2(D[1],Q[1],clrb,clk,enable), U3(D[2],Q[2],clrb,clk,enable), U4(D[3],Q[3],clrb,clk,enable); endmodule module dff_counter(