EDA第4章VHDL概述与基本结构(4.1-4.2).pptVIP

4.1 VHDL概述 1、什么是VHDL、有何优点 2、怎样用VHDL描述数字电路 3、学习VHDL应了解那些知识 1、What is VHDL Very high speed integrated Hardware Description Language (VHDL) is an industry standard hardware description language description the hardware in language instead of graphic easy to modify easy to maintain very good for complex combinational logic BCD to 7 Segment converter address decoding state machine more than you want…….. What VHDL Standard means? The VHDL is used to describe Inputs port Outputs port behavior and functions of the circuits Altera VHDL（ Max+Plus II 综合器） Altera Max+Plus II support both VHDL 1987 and 1993 Max+Plus II only support SUBSET of the two IEEE standard Detail of the support can be referred to Altera Max+Plus II VHDL handbook on page 89 Section 3 Why I use VHDL instead of Graphic Easy to Modify It is more powerful than Graphic VHDL is a portable language because is device independent the same code can be applied to Device manufactured by Company A or Company B Graphic vs VHDL Graphic is what you draw is what you get “tell me what hardware you want and I will give it to you” VHDL is what you write is what functional you get “ tell me how your circuit should behave and the VHDL compiler will give you the hardware that does the job” but the designer can not control how the circuit implement VHDL在电子系统设计中的应用 VHDL在电子系统设计中的应用 电子系统设计的描述等级 1、行为级 2、RTL级（Register transfer level） 3、逻辑门级 4、版图级 用VHDL可以描述以上四个等级 VHDL在电子系统设计中的应用 VHDL在电子系统设计中的应用 VHDL在电子系统设计中的应用 VHDL在电子系统设计中的应用 2、怎样用VHDL描述数字电路 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux21 IS PORT (a,b:IN STD_LOGIC; S: IN STD_LOGIC Y:OUT STD_LOGIC); END ENTITY MUX21; ARCHITECTURE behavor OF mux21 IS BEGIN y=a WHEN s=0 ELSE b ; END ARCHITECTURE behavor; 示例二 锁存器 （时序电路） LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY latch1 IS PORT ( D:IN STD_LOGIC; CLK: IN STD_LOGIC; Q:OUT STD_LOGIC); END ENTITY latch1; ARCHITECTURE behavor OF latch1 IS SIGNAL sig_save:STD_LOGIC; BEGI