高性能处理器31.pptVIP

1/20/05 USTC CS AN Hong 结构相关：由访存引起的结构相关 结构相关的解决方案：阻塞 控制相关： What’s the Problem? Control Hazard Solution #1: Stall Stall: wait until decision is clear Impact: 2 lost cycles (i.e. 3 clock cycles per branch instruction) = slow Move decision to end of decode save 1 cycle per branch Control Hazard Solution #2: Predict Predict: guess one direction then back up if wrong Impact: 0 lost cycles per branch instruction if right, 1 if wrong (right - 50% of time) More dynamic scheme: history of 1 branch (- 90%) Control Hazard Solution #3: Delayed Branch Delayed Branch: Redefine branch behavior (takes place after next instruction) Impact: 0 clock cycles per branch instruction if can find instruction to put in “slot” (- 50% of time) As launch more instruction per clock cycle, less useful Data Hazard on R1 Read After Write (RAW) InstrJ tries to read operand before InstrI writes it  Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication. Data Hazard on r1: Read after write hazard (RAW) Data Hazard on r1: Read after write hazard (RAW) Dependencies backwards in time are hazards Data Hazard Solution: Forwarding “Forward” result from one stage to another  Forwarding (or Bypassing): What about Loads? Dependencies backwards in time are hazards Data Hazard Even with Forwarding Can’t solve with forwarding ，Must delay/stall instruction dependent on loads Forwarding (or Bypassing): What about Loads ? Dependencies backwards in time are hazards Data Hazard Even with Forwarding Can’t solve with forwarding ，Must delay/stall instruction dependent on loads Software Scheduling to Avoid Load Hazards Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,Ra SUB Rd,Re,Rf SW d,Rd Data Hazard Solution(3):Out-of-Order Execution Need to detect data dependences at run time Need of precise exceptions: Out-of-order execution, in-order completion Data Hazard Solution(4): Data Speculation In a wide-issue