EDA 课件7.pdf

1 A/D D/A 2 3 —— 4 5 EP2C5 FPGA 150 6 1.FPGA/CPLD MAX II EPM240 CPLD 46 7 2. 8 FPGA/CPLD 9 10 11 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity matrikeyscan is port( clk : in std_logic; col : in std_logic_vector(3 downto 0); row : out std_logic_vector(3 downto 0); keyout : out std_logic_vector(3 downto 0)); end matrikeyscan; architecture behave of matri