电子科大201数字电路期中考试.docVIP

电子科技大学二零零九年至二零一零学年第二学期 “数字逻辑设计及应用”课程考试题（半期）（120分钟） 考试日期2011年4月23日 一 二 三 四 五 六 七 八 九 十 总分 评卷教师 I. To fill the answers in the “( )” (2’ X 19=38) 1. [1776 ]8 = ( 3FE )16 = ( 1111111110 )2= ( 1000000001 ) Gray . 2. (365)10 = ( 001101100101 )8421BCD ＝( 001111001011 ) 2421 BCD. 3. Given an 12-bit binary number N. if the integer’s part is 9 bits and the fraction’s part is 3 bits ( N = a8 a7 a6 a5 a4 a3 a 4. If X’s signed-magnitude representation XSM is（110101）2, then it’s 8-bit two’s complement representation X2’s COMP is( ) , and (–X)’s 8-bit complement representation (–X) 2’s COMP is ( )2 5. If there are 2011 different states, we need at least ( 11 ) bits binary code to represent them. 6. If a positive logic function expression is F=AC’+B’C(D+E)，then the negative logic function expression F = ( (A+C’)(B’+(C+DE)) ). 7. A particular Schmitt-trigger inverter has VILmax = 0.7 V, VIHmin = 2.1 V, VT+ = 1.7 V, and VT-= 1.3 V, VOLmax=0.3V, VOHmin=2.7V. Then the DC noise margin in the HIGH state is ( 0.6V ), the hysteresis is ( 0.4V ). Fig.1 Circuit of problem I-88. The unused CMOS NAND gate input in Fig. 1 should be tied to logic ( 1 ). Fig.1 Circuit of problem I-8 9. If number [ A ] two’s-complement and [ B] two’s-complement, calculate [-A-B ] two’s-complement, [-A+B ] two’s-complement and indicate whether or not overflow occurs. [-A-B ] two’s-complement=[ ], overflow: [ yes ] [-A+B ] two’s-complement=[ ], overflow: [ no ] .10. The following logic diagram Fig.2 implements a function of 3-variable with a 74138. The logic function can be expressed as F (A,B,C) = ∑A,B,C ( 0,1,2 ). Fig.2 Circuit of problem I-10 评分基本标准： 每空1分，错则全扣。 II. There is only one correct answer in the following questions.(3’ X 9 = 27) 1. Which of the following Boolean equations is NOT correct? ( B ) A) A+0=A B) A?1 = A