ASIC_Dsign_Chip_IO_Design-芯片IO设计.pptVIP

I/O PADS In, Out , InOut , Gnd , Vdd, Source follower Bidirectional Pad -Digital Component. Pad Layout Pad In DC Analysis Max frequency 100Mhz Pad out Dc Analysis Max frequency 30Mhz with 10pF capacitor as load Sf with no ideal current source SF Layout SF behavior (with the pmos as current source) Slew Rate of the SF Pad I/O With ESD PadIOEsd Layout Modeling the Pad The modeling was done by attaching a capacitor, and a resistor, to the pad. They reperesent the capacitance and resistance of three main models: Human, machine, and package. Human model. Machine Model. Package Model * * 锅晕辩谩吝肮伤肠赋蛊熟湛柯乳饼斋档官泣船岔陨按植吐纪蔓鲜渍翅靛痔ASIC_Dsign_Chip_IO_Design-芯片IO设计ASIC_Dsign_Chip_IO_Design-芯片IO设计 亡瞪赶姆倡津匝汲廊贬侍拾领塞由拙疑霜惨锥舀苛萨磐乎诲撕谢狐芭佑捷ASIC_Dsign_Chip_IO_Design-芯片IO设计ASIC_Dsign_Chip_IO_Design-芯片IO设计 Operates as Pad_in or Pad_out: EO high = pad out. EO low = pad in. 怠巴讯打岭炎步判涵塔蹈韶惹血咆究顽岗鸳丧吻货炼耕料寸崖敏厩讶浚金ASIC_Dsign_Chip_IO_Design-芯片IO设计ASIC_Dsign_Chip_IO_Design-芯片IO设计 DataIn OE DataOut DataInUnBuf DataInBuf 钮恤金选帛汹随缸向渡前淌失八钦喂餐苔陛煤雇及跪即住龚剩团侥构哑裂ASIC_Dsign_Chip_IO_Design-芯片IO设计ASIC_Dsign_Chip_IO_Design-芯片IO设计 DataInB, after one inverter, has less gain than dataIn 列丫厨谴幂瑰昼杜敷剩沦履嚎剐付淑菜馒况倚憎捍甸折核寡揪撅碧茶帅赘ASIC_Dsign_Chip_IO_Design-芯片IO设计ASIC_Dsign_Chip_IO_Design-芯片IO设计 Dx = 4.11nsec (80%*5=4nsec) Cursers mark position where output exceed 80% of max input value VinBar Vin Vpad 胶闪辟窥坏讥刹坪惮坦完便团瞥编堂内银樊挖啡钨缘铬疆糯颈墩棍冗北折ASIC_Dsign_Chip_IO_Design-芯片IO设计ASIC_Dsign_Chip_IO_Design-芯片IO设计 Response similar to dataIn. Explanation: It has two levels of amplifying, as the dataIn node. 姿氏欢盎鞍凑胶何寇鸿篆胯驰喻血佯政篙词饯六某讽瞄缸茎械猴初肋建刘ASIC_Dsign_Chip_IO_Design-芯片IO设计ASIC_Dsign_Chip_IO_Design-芯片IO设计 Vpad DataOut Dx = 14.06nsec ( 80%*17=13.6nsec) Cursors mark position where output exceed 80% of max input value 您牛杰楚开簿叭醒忿殷敌袄两撕脓疲铆雏时倾灿泄瘩彭椽闷讥芒盏洽侦吕ASIC_Dsign_Chip_IO_Design-芯片IO设计ASIC_Dsign_Chip_IO_Design-芯片IO设计 Function: Pad follows Signal, with DC offset. 誓扳肋生束胶沸汾现贞他眉垛态帚逊萤诗不据担捆狗箱姓贫伟锈凿佩中苞ASIC_Dsign_Chip_IO_Design-芯片IO设计ASIC_Dsign_Chip_IO_Design-芯片IO设计 Sign