时序敏感的3D IC绑定优化方法 - 计算机体系结构国家重点实验室.PDFVIP

22 11 Vol. 22 No. 11 2010 11 Journal of ComputerAided Design Computer Graphics Nov. 2010 3D IC 1, 2) 2) 2) 2) 2) 1) 王 杰 张 磊 李华伟 韩银和 李晓维 梁华国 , , , , , 1) ( 230009) 2) ( , 100190) ( hfut_jie_w ang@ sina. com) : 3D IC ., 3D IC . , , ! !; , , . , , 3D IC . : 3D IC; ; ; ; : T P303 A TimingAware 3D IC Bonding Optimization Method 1, 2) 2) 2) 2) 2) 2) Wang Jie , Zhang Lei , Li Huawei , Han Yinhe , Li Xiaowei , and Liang Huaguo 1) (School of Comp uter and I nf or mation, H ef ei University of Technology , H ef ei 230009) 2) (K ey L aboratory of Comp uter Sy stem and rchitecture, Institute of Comp uting Technology , Chinese cademy of Sciences, Beij ing 100190) Abstract: U nder impacting of process variation, the yield of the 3D IC mostly depends on the bonding strategies. In order to reduce the yield loss due to unmerited bonding orders, this paper proposes a bonding optimization method based on critical path delay to improve the yield in 3D chips bonding process. Path delay measurement is employed to obtain the timing characteristics of the prebond chips; and the chip with long paths is bonded to the one with short paths in different layers, which means use good one to save bad one. Two matching algorithms called grading and toothing are presented by formalizing the max yield problem with bipartite graph maximum matching model. Experimental results show that the proposed bonding method achieved much higher yield compared to random bonding. Key words: 3D IC; bonding; delay measurement; c