THC63LVDM63A元件资料.pdfVIP

www.DataSheet4U.com Version 2.10 THine PRELIMINARY THC63LVDM63A/THC63LVDF64A 85MHz LVDS 18 Bit COLOR HOST-LCD PANEL INTERFACE General Description Features The THC63LVDM63A transmitter converts 21 21:3 Data channel compression at up to bits of CMOS/TTL data into LVDS(Low 223 Megabytes per sec throughput Voltage Differential Signaling) data stream. A Wide Frequency Range: 20 - 85 MHz phase-locked transmit clock is transmitted in suited for VGA,SVGA,XGA and SXGA parallel with the data streams over a fourth Narrow bus (8 lines) reduces cable size LVDS link. The THC63LVDM63A can be 345mV swing LVDS devices for programmed for rising edge or falling edge Low EMI clocks through a dedicated pin. Supports Spread Spectrum Clock Generator The THC63LVDF64A receiver convert the On chip Input Jitter Filtering LVDS data streams back into 21 bits of PLL requires No External Components CMOS/TTL data with falling edge clock. At a Single 3.3V supply with 110mW(TYP) transmit clock frequency of 85MHz, 18 bits of Low Power CMOS Design RGB data and 3 bits of LCD timing and control Power-Down Mode data (HSYNC, VSYNC, CNTL1) are Low profile 48 Lead TSSOP Package transmitted at a rate of 595 Mbps per LVDS data Clock Edg