VPR：一种新的包装布局和布线工具的FPGA研究外文文献.docVIP

毕业设计(论文)外文资料翻译 系 别： 电子信息系 专 业： 通信工程 班 级： B090310 姓 名： 马佳妮 学 号： 外文出处： www.CNKI.com 附 件： 1. ； 2. 2013年3月20日外文原文 VPR: A New PackingPlacement and Routing Tool for FPGA Research1 Abstract We describe the capabilities of and algorithms used in a new FPGA CAD tool，Versatile Place and Route (VPR). In terms of minimizing routing area， VPR outperforms all published FPGA place and route tools to which we can compare.Although the algorithms used are based on previously known approaches， we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today’s industrial designs.VPR is capable of targeting a broad range of FPGA architectures， and the source code is publicly available. It and the associated netlist translation clustering tool VPACK have already been used in a number of research projects worldwide， and should be useful in many areas of FPGA architecture research. Introduction In FPGA research， one must typically evaluate the utility of new architectural features experimentally. That is， benchmark circuits are technology mapped，placed and routed onto the FPGA architectures of interest， and measures of the architecture’s quality， such as speed or area， can then readily be extracted. Accordingly， there is considerable need for flexible CAD tools that can target a wide variety of FPGA architectures efficiently， and hence allow fair comparisons of the architectures.This paper describes the Versatile Place and Route (VPR) tool， which has been designed to be flexible enough to allow comp