vhdl基本语素、语法、语句(杨).pptVIP

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * S0 S2 0/0 1/0 S1 1/0 0/1 0/0 1/0 Mealy型序列信号检测器—状态图 序列信号：110 S x/Z ‘1’ ‘11’ S0/0 S2/0 0 1 S1/0 1 0 1 Moore型序列信号检测器—状态图 序列信号：110 S/Z x ‘1’ ‘11’ S3/1 ‘110’ 0 0 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY sqs IS PORT( x,clk: in Std_logic; z: out Std_logic); END sqs; Mealy型-VHDL代码转换 ARCHITECTURE a OF mealy IS TYPE STATE_TYPE IS (s0, s1, s2); SIGNAL state: STATE_TYPE; BEGIN Mealy型-VHDL代码转换 PROCESS (clk) BEGIN If （clk’EVENT AND clk = ‘1’） then CASE state IS WHEN s0 = IF din=‘1’ THEN state = s1; else state=s0; END IF; WHEN s1 = IF din=‘1 THEN state = s2; else state=s0; END IF; WHEN s2 = IF din=0 THEN state=s0; else state=s2; END IF; WHEN others = state=s0; END CASE; End if; END PROCESS; z=1 when (state=s2 and din=’0’) else 0; --输出不仅与状态有关，而且和输入有关。 END a; Mealy型-VHDL代码转换 I. Mealy型 Mealy型-VHDL代码转换标准形式 P0: PROCESS (clk) BEGIN IF clkevent and clk=1 THEN current_state=excitation; END IF; END PROCESS p0; P1: PROCESS(current_state,in1) BEGIN CASE current_state IS WHEN s0 = IF in1=1 THEN excitation=s1; END IF; WHEN s1 = IF in1=0 THEN excitation =s2; END IF; WHEN s2 = IF in1=1 THEN excitation =s3; END IF; WHEN s3 = IF in1=0 THEN excitation =s0; END IF; END CASE; END PROCESS p1; I. Mealy型 Mealy型-VHDL代码转换标准形式 P2: PROCESS(current_state,in1) BEGIN CASE current_state IS WHEN s0 = IF in1=1 THEN y=‘0’; END IF; WHEN s1 = IF in1=0 THEN y=‘0’; END IF; WHEN s2 = IF in1=1 THEN y=‘0’ ; END IF; WHEN s3 = IF in1=