硬件描述语言(VHDL)十字路口交通灯.docVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jiaotongdeng is port( clk_in:in std_logic; rst:in std_logic; light:out std_logic_vector(7 downto 0); zhug:out STD_LOGIC_VECTOR(6 downto 0); zhus:out STD_LOGIC_VECTOR(6 downto 0); zhig:out STD_LOGIC_VECTOR(6 downto 0); zhis:out STD_LOGIC_VECTOR(6 downto 0)); end jiaotongdeng; architecture a of jiaotongdeng is type states is(green_red,yellow_red,red_green,red_yellow); signal state:states:=green_red; signal nextstate:states:=green_red; signal dzhig:integer range 0 to 9; signal dzhis:integer range 0 to 3; signal dzhug:integer range 0 to 9; signal dzhus:integer range 0 to 2; signal clock_buffer:std_logic; signal count_time:integer range 0 to 1999999; signal clk:std_logic; signal seczhig:integer range 0 to 9 ; signal seczhis:integer range 0 to 3 ; signal seczhug:integer range 0 to 9 ; signal seczhus:integer range 0 to 2 ; begin frequent:process(clk_in) begin if clk_inevent and clk_in=1 then if count_time=1999999 then count_time=0; clock_buffer=not clock_buffer; else count_time=count_time+1; end if; end if; clk=clock_buffer; end process; light_statment:process(rst,state) begin if rst=0 then light NEXTSTATE=YELLOW_RED; else case state is when green_red = light nextstate=yellow_red; dzhus=0; dzhug=4; dzhis=0; dzhig=4; when yellow_red = light nextstate=red_green; dzhus=2; dzhug=4; dzhis=1; dzhig=9; when red_green =light=0111