OrCAD 利用文件快速产生一颗多pin数的零件及如何分割零件.pdfVIP

◆OrCAD 利用文件快速產生一顆多pin 數的零件及如何分割零件 一般大家在產生PIN 腳數眾多的零件上面，一直都是令人一個頭痛的問題。 因為要考慮規劃零件例如:如何分割零件，還有最令人感到麻煩的是在產生零 件時，PIN 腳的名稱還有Pin Number 的輸入問題，今天就讓我們用一點小 技巧來讓你不再感到困擾。 ．Date ： 2005/ 04 /11 ．Author ：Addi ．Revision ： 1 ．Version ： 10.3 ．備註: .tw (一)快速建立PIN 腳數眾多的零件 當我們要建立多pin 數的元件，若要從無到有建立出來的時候，一般都會感到很辛苦。Capture 在 此提供Generate Part 的功能，幫助User 來建立元件。 下面是Capture 可支援的格式，等一下我們簡單的舉例子來說明: 以Xilinx 的Pin file 來產生元件。 • Actel Pin File. This file is typically created by the Actel Designer tool. • Altera Pin File. This file is created by the Altera MAX+PLUS II. • Capture Schematic/Design. A source design or library file from an external file or from the current design. This is automatically set when a schematic folder, which is in a design (.DSN) file or library (.OLB) file, is selected in the project manager at the time the Generate Part dialog box is opened. • EDIF Netlist. Alteras MAX+PLUS II tool generates an EDIF netlist. You can also use EDIF files from any other source to generate a symbol. • Lattice JEDEC File. This file is created by Lattice ISP products • Lattice Pin File. This file is created by the Lattice ispExpert tool. • Lucent ORCA Pad File. This file is created by the Lucent ORCA tool. • PSpice Model Library. Used by the PSpice simulator. You can create your own PSpice model libraries using the PSpice Model Editor or use the model libraries that ship with PSpice and install in the Library directory. • Verilog Netlist. Used for board simulation and for FPGA projects. You can use these netlists to generate a symbol. • VHDL Netlist. Some vendor tools generate VHDL netlists (with embedded timing information) during place and route. You can use these netlists to generate a symbol. • Xilinx M1 Pad File. This file is created by the Xilinx M1 tool. • Xilinx P