Attiny 44A 总结资料.docVIP

Attiny 44A 总结 端口信息 Generic Description of Overriding Signals for Alternate Functions 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The reset pin can also be used as a (weak) I/O pin. 1.1.5 Port A (PA7:PA0) PA口是带有内部上拉电阻的8位双向I/O口（可以选择每一位是否带上拉电阻）。如果带有上拉电阻，低电平为PA口的输入。 概述 CPU内核 它拥有32个八位工作寄存器组ALU – Arithmetic Logic Unit，Status Register Reset and Interrupt Handling 优先级顺序最高的是RESET，然后是外部中断0. -SEI(); /* set Global Interrupt Enable */设置全局中断使能 _SLEEP(); /* enter sleep, waiting for interrupt */进入休眠模式，等待中断 Register Description SREG – AVR Status Register I：全局中断使能；T：位复制存储；H：低四位进位标志；S：标志位（S= N ⊕ V）； V：溢出标志位；N：负标志位；Z：零标志位；C：进位标志位。 4. Memories Clock System Clock Subsystems：CPU Clock – clkCPU；I/O Clock – clkI/O；Flash Clock – clkFLASH；ADC Clock – clkADC。 Clock Sources Note: 1. For all fuses “1” means unprogrammed and “0” means programmed. External Clock Calibrated Internal 8 MHz Oscillator Internal 128 kHz Oscillator Low-Frequency Crystal Oscillator Crystal Oscillator / Ceramic Resonator Register Description OSCCAL – Oscillator Calibration Register CLKPR – Clock Prescale Register Bit7: 时钟分频使能位；Bit3-Bit0:时钟分频选择位： 0000 不分频； 0001 2分频； 0010 4分频； 0011 8分频； 0100 16分频； 0101 32分频； 0110 64分频；0111 128分频； 1000 256分频； 其他保留。 Power Management and Sleep Modes 6.1 Sleep Modes Register Description Bit 7 – BODS: BOD Sleep；Bit 5 – SE: Sleep Enable；Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1 and 0；? Bit 2 – BODSE: BOD Sleep Enable；Bit1：0—时钟选择。 PRR – Power Reduction Register Bit 3 – PRTIM1: Power Reduction Timer/Counter1；Bit 2 – PRTIM0: Power Reduction Timer/Counter0；? Bit 1 – PRUSI: Power Reduction USI；Bit 0 – PRADC: Power Reduction ADC System Control and Reset Resetting the AVR 复位源：上电复位；外部复位；看门狗复位；掉电复位。 Register Description MCUSR – MCU Status Register Bit 3 – WDRF: Watchdo