0 R XC9572XL High Performance CPLD - All （0 R XC9572XL高性能CPLD -所有）.pdf

0 R XC9572XL High Performance CPLD DS057 (v2.0) April 3, 2007 0 0 Product Specification Features cations and computing systems. It is comprised of four • 5 ns pin-to-pin logic delays 54V18 Function Blocks, providing 1,600 usable gates with • System frequency up to 178 MHz propagation delays of 5 ns. See Figure 2 for overview. • 72 macrocells with 1,600 usable gates Power Estimation • Available in small footprint packages Power dissipation in CPLDs can vary substantially depend- - 44-pin PLCC (34 user I/O pins) ing on the system frequency, design application and output - 44-pin VQFP (34 user I/O pins) loading. To help reduce power dissipation, each macrocell - 48-pin CSP (38 user I/O pins) in a XC9500XL device may be configured for low-power - 64-pin VQFP (52 user I/O pins) mode (from the default high-performance mode). In addi- - 100-pin TQFP (72 user I/O pins) tion, unused product-terms and macrocells are automati- - Pb-free available for all packages cally deactivated by the software to further conserve power. • Optimized for high-performance 3.3V systems For a general estimate of ICC, the following equation may be - Low power operation