EDA实代码Verilog.doc

实验一、五人表决器 (1)vote5.v ①方案一 `timescale 1ns / 1ps module vote5( input a,b,c,d,e, output f ); assign f=abc||abd||abe||acd||ace|| ade||bcd||bce||bde||cde; endmodule ②方案二 module vote5(a,b,c,d,e,f); input a,b,c,d,e; output f; reg f; reg[2:0] count1; initial count1=0; always@(a,b,c,d,e) begin count1=a+b+c+d+e; f=count13?0:1; end endmodule (2)test.v module test; reg a; reg b; reg c; reg d; reg e; wire f; vote5 uut ( .a(a), .b(b), .c(c), .d(d), .e(e), .f(f) ); initial begin a = 0; b = 0; c = 0; d = 0; e = 0; #100 a = 1; b = 0;