chip synthesis芯片综合课件.ppt

Chip Synthesis;Agenda Introduction to Synthesis Partitioning for Synthesis Coding for Synthesis Timing and Area Environmental Attributes Time and Load Budgeting Timing Analysis Compiling a Hierarchical Design Compiling a Large Design Conclusion;Synthesis is the transformation of an idea into a manufacturable device to carry out an intended function Designers have synthesized circuits for years---by hand Transformation from abstract to concrete;Levels of Abstraction;For EDA, Synthesis is …;Why Synthesis?;Synthesis is Constraint-Driven;Synthesis is Path-based;;Chip Synthesis Process;Tools for Chip Synthesis;Tools for Chip Synthesis – cont.;A technology library contains a set of primitive cells which be used by DC to build a circuit The timing and electrical characteristics of these cells Net delay and net parasitic information Definition of capacitance, time and resistance units Technology libraries are created by vendor; Target Library set target_library {smic_018.db} Link Library set link_library {* smic_018.db dw_foundation.sldb} Synthetic Library set synthetic_library { dw_foundation.sldb} Symbol Library set symbol_library { smic018.sdb} Search Path set search_path [list . ${smic_std_cell} ];Agenda Introduction to Synthesis Partitioning for Synthesis Coding for Synthesis Timing and Area Environmental Attributes Time and Load Budgeting Timing Analysis Compiling a Hierarchical Design Compiling a Large Design Conclusion;Partitioning is the process of dividing complex designs into smaller parts;Partitioning is driven by many needs: Separate distinct functions Achieve workable size and complexity Manage project in team environment Design Reuse Meet physical constraints And many, many others….;What do we gain by “partitioning for synthesis”: Better results – smaller and faster design Easier synthesis process – simplified constraints and scripts Faster compiles – quicker turnaround;module ADR_BLK (…); DEC U1 (ADR, CLK, INST); OK U2 (ADR, CLK, AS, OK1