011BDLC.PPT课件.ppt

BYTE DATA LINK CONTROLLER (BDLC ) ;Internal Bus;BDLCCONTROLLER;BDLC Block Diagram;OPERATING MODES;BDLC BLOCK DIAGRAM;CPU Interface: contains software addressable registers and provides link between HCS12 CPU and Buffers;Ignore Message (IMSG) Disables receiver until new Start of Frame (SOF) is detected Cleared automatically by reception of SOF symbol or a BREAK symbol It then generates interrupt requests and will allow changes to the status register to occur All BDLC interrupt requests will be masked when this bit is set 1 = Disable Receiver 0 = Enable Receiver Clock Select (CLKS) Selects BDLC Nominal Frequency (fbdlc) 1 = Binary frequency (1.048576 MHz) is used for fbdlc 0 = Integer frequency (1 MHZ) is used for fbdlc Rate Select (R1, R0) Determines the amount by which the frequency of the MCU system clock signal (fTCLKS) is divided to form the MUX Interface clock (fbdlc) Defines the basic timing resolution of the MUX Interface Interrupt Enable (IE) 1 = Enable Interrupt requests from BDLC 0 = Disable Interrupt requests from BDLC;BDLC Rate Selection;State Machine Reset (SMRST) 1 = Arms the state Machine but does not reset BDLC 0 = Clearing SMRST after it has been set, causes BDLC to reset Digital Loopback Mode (DLOOP) Determines the source to which RXPD is connected and can be used to isolate bus fault conditions 1 = RxPD is connected to TxPD, BDLC is now in Digital Loopback Mode 0 = RxPD is connected to RxPA, BDLC is taken out of Digital Loopback Mode Receive 4X Enable (RX4XE) Determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps 1 = BDLC is put in 4X receive only operation 0 = BDLC transmits and receives at 10.4 kbps Rx4x4 Defines the basic timing resolution of the MUX Interface;BDLC Frame Format;Transmit In-Frame Response Control (TSIFR, TMIFR1, TMIFR0);BDLC State Vector Register;BDLC Data Register Used to pass the data to be transmitted to the J1850 bus f