soc中的伪双口ram优化设计方法及应用-计算机辅助设计与图形学.pdf

第29 卷 第2 期 计算机辅助设计与图形学学报 Vol. 29 No.2 2017 年2 月 Journal of Computer-Aided Design Computer Graphics Feb. 2017 SoC 中的伪双口RAM 优化设计方法及应用 1) 2) 周清军 , 刘红侠 1) (西安培华学院中兴电信学院 西安 710125) 2) (西安电子科技大学宽禁带半导体材料与器件教育部重点实验室 西安 710071) (zhqj76@126.com) : 针对 SoC 中TP RAM 的面积及功耗较大问题, 提出一种优化设计方法. 该方法将 SoC 中的TP RAM 替换成 SP RAM, 并在 SP RAM 外围增加读写接口转换逻辑, 使替换后的RAM 实现原TP RAM 的功能, 以保持对外接口不 变. 将文中方法应用于一款多核 SoC 芯片, 该芯片经TSMC 28 nm HPM 工艺成功流片, die size 为 10.7mm ×11.9mm, 功耗为 17.2W. 测试结果表明, 优化后的RAM 面积减少了24.4%, 功耗降低了39%. ：伪双口RAM; 单口RAM; 功耗优化; 面积优化; 接口转换逻辑 ：TN402 Optimization of Two Port RAM in SoC and its Application Zhou Qingjun1) and Liu Hongxia2) 1) (ZTE Telecom College, Xi’an Peihua University, Xi’an 710125) 2) (Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi’an 710071) Abstract: As the area and power consumption of TP RAM in SoC are large, a new design method of optimization is proposed. In order to achieve the function of the original TP RAM and keep the external interface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of conversion are added around SP RAM. The method proposed in this paper is used in the multi core SoC chip which has been successfully taped out in TSMC 28 nm HPM process. The chip occupies 10.7 mm×11.9 mm of die area and consumes 17.2 W. The testing results indicate that the area of optimized RAMs is reduced by 24.4%, and the power saving is 39%. Key words: two port RAM; single port RAM; optimization of power consumption; area optimization; interface logics of conversion , random RAM , SoC . access memory, RAM)(system on chip, TP RAM , SoC SoC), RAM SoC