design of an all-digital synchronized frequency multiplier based on a dual-loop (dfll) architecture设计一个全数字同步倍频器基于dual-loop(外国语文学系)体系结构.pdfVIP

Hindawi Publishing Corporation VLSI Design Volume 2012, Article ID 546212, 7 pages doi:10.1155/2012/546212 Research Article Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture Maher Assaad and Mohammed H. Alser Department of Electrical and Electronics Engineering, University Technology of PETRONAS (UTP), Perak, 31750 Tronoh, Malaysia Correspondence should be addressed to Maher Assaad, maher assaad@.my and Mohammed H. Alser, mohammed.hk g01558@.my Received 2 March 2012; Revised 18