design of an inter-plane circuit for clocked plas以塑料inter-plane电路的设计.pdfVIP

VLSI Design, 2002 Vol. 14 (4), pp. 373–381 Design of an Inter-plane Circuit for Clocked PLAs CHUA-CHIN WANG*, YA-HSIN HSUEH, YU-TSUN CHIEN and YING-PEI CHEN Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan (Received 1 May 2000; Revised 16 March 2001) Since the Programmable Logic Arrays (PLAs) can implement almost any Boolean function, they have become popular devices in realization of both co