testability synthesis for jumping carry adders可测试性合成为跳蛇.pdfVIP

VLSI Design, 2002 Vol. 14 (2), pp. 155–169 Testability Synthesis for Jumping Carry Adders CHIEN-IN HENRY CHENa,* and MAHESH WAGHb aDepartment of Electrical Engineering, Wright State University, Dayton, OH 45435, USA; bLSI Logic, Milpitas, CA 95035, USA (Received 27 June 1999; In final form 4 February 2000) Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don’t ca