讯号阻抗耦合验证–sigrityerc.pdfVIP

訊號阻抗耦合驗證– Sigrity ERC Addi Lin / Graser 2 / Sep / 2016 Topic • What’s OrCAD Sigrity ERC? • OrCAD Sigrity ERC – Trace Reference Check – Trace Coupling Check – Trace Impedance Check • OrCAD Sigrity SRC • Summary What’s OrCAD Sigrity ERC? • OrCAD® Sigrity™ Electrical Rules Check (ERC) 可使PCB 設計師快速篩選PCB 設計的信號品質 ，而無需給予任何模 擬模型 ，或者是一個完整信號。 – 超越DRC 檢查規範 – 為PCB 設計找出阻抗不連續 – 進行layout 走線串擾評估 OrCAD Sigrity ERC 可以不須依賴的SI 工程師，在PCB 佈局階段即可以發 現信號質量問題 ，進而提升產品設計效率以達到縮短整體設計時間。 OrCAD Sigrity ERC Layout 阻抗與串擾問題 • Talk about impedance Z0, let’s see the following case: – After simulation, you set the trace width to be 5 mil in the constraint system to achieve the impedance you want. Of course, the following picture will show no DRC violation. But if this is a 2-layers design and… PWR1 TOP Bottom 5 mil GND PWR 1 PWR1 1. Coplarar reference 1. Layer Transistion 1. Reference change 2. Cross plane split ERC – 走線上／下層面的 參考電源層 • Based on upper / lower layer references – Trace9047  one section – Trace9048  5 sections trace9048 ERC results Note: This is the reason why there are 5 impedance sections. 走線參考電源層檢查 • Trace cross layer reference shows the net names for the reference p