The SSD Endurance Race Flash Memory Summit（SSD耐力赛闪存峰会）.pdfVIP

The SSD Endurance Race: Who’s Got the Write Stuff? Ulrich Hansen Director of Market Development Santa Clara, CA August 2012 1 © 2012 HGST, a Western Digital company Write Endurance – Why it Exists … • Programming and erasing of a typical NAND cell involves forcing charge carriers through the dielectric isolators onto the floating gate via a tunneling effect • This introduces ‘wear’ in the dielectric materials, e.g. by trapping / detrapping of charges in the materials and other defects • With more and more program and erase activity, ‘wear’ decreases the isolating properties of the dielectric and changes its tunneling effectiveness, ultimately resulting in: • Incorrect reads from the NAND cell after relatively short retention times • Program / erase failures Santa Clara, CA August 2012 2 © 2012 HGST, a Western Digital company NAND Component Endurance: Program Erase Cycles • NAND component endurance is specified an number of Program/Erase cycles under certain specifications and testing conditions • Meet Bit Error Rate under certain controller ECC capability assumptions and data retention specifications • Most test conditions are defined in JEDEC standards • NAND Flash types and factory optimizations can create various endurance levels • NAND Factory optimizations include trimming, settings, and sorting binning • Typical P/E specifications for 3Xnm and 2Xnm NAND generations • SLC: 100K – 200K P/E cycles • eMLC: 10K –