VLSI ARCHITECTURE Guru Gobind Singh （VLSI架构大师高宾德辛格）.doc

Course Structure Scheme For Master of Technology In VLSI Design Guru Gobind Singh Indraprastha University Kashmere Gate, Delhi – 6 [INDIA] www.ipu.ac.in  Eligibility Condition 1. B. Tech / B.E in Electronics Communication / Electronics / Computer Science/Information Technology or equivalent degree with 60% marks. 2. MSc (Electronics) with 60% marks. Admission Procedure Admission will be made on the basis of GATE score in the relevant field. If seats remain vacant after admitting the students with valid GATE score, then the admission will be made on the basis of merit of the qualifying marks subject to minimum 60% marks in the qualifying degree. SCHEME OF EXAMINATION M.Tech. (VLSI Design) First Semester Examination Course Code Subject Name L/P Credits Theory Papers ITV-601 Advanced Computer Architecture 3 3 ITV-603 VLSI Technology 3 3 ITV-605 MOS Circuit Design 3 3 ITV-607 Solid State Electronics Devices 3 3 ITV-609 Digital System Design 3 3 ITV-611 Data Structure Algorithm Analysis 3 3 Practicals/Viva-voce ITV-651 Lab – I 4 2 ITV-653 Lab – II 4 2 ITV-655 Lab - III 4 2 Total 30 24 SCHEME OF EXAMINATION M.Tech. (VLSI Design) Second Semester Examination Course Code Subject Name L/P Credits Theory Papers ITV-602 Analog VLSI Design 3 3 ITV-604 Computational Methods 3 3 ITV-606 Digital Signal Processing 3 3 Electives (Choose any TWO) ITV-608 CMOS RF Circuit Design 3 3 ITV-610 VLSI Test Testability 3 3 ITV-612 Low Power VLSI Design 3 3 ITV-614 Cluster Grid Computing 3 3 ITV-616 Embedded System Design 3 3 ITV-618 Designing with ASICS 3 3 ITV-620 Real Time System Software 3 3 ITV-622 Neural Networks 3 3 ITV-624 Digital Logic with Verilog 3 3 ITV-626 Microwave Optoelectronic Devices 3 3 ITV-628 Project Work 3 3 Practicals/Viva-voce ITV-652 Lab – IV 4 2 ITV-654 Lab – V 4 2 ITV-656* Minor Project - I 4 4 Total 27 23 * NUES - Non University Exam System SCHEME OF EXAMINATION M.Tech. (VLSI Design) Third Semester Ex