第10章节VHDL基本语句.ppt

* 10.2 并行语句 10.2.10 生成语句 图10-3 生成语句产生的8个相同的电路模块 * 10.2 并行语句 10.2.10 生成语句 【例10-26】锁存器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Latch IS PORT( D，ENA : IN STD_LOGIC; Q : OUT STD_LOGIC ); END ENTITY Latch ; ARCHITECTURE one OF Latch IS SIGNAL sig_save : STD_LOGIC; BEGIN PROCESS (D, ENA) BEGIN IF ENA = 1 THEN sig_save = D ; END IF ; Q = sig_save ; END PROCESS ; END ARCHITECTURE one; * KX康芯科技 【例10-27】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SN74373 IS PORT (D : IN STD_LOGIC_VECTOR( 8 DOWNTO 1 ); OEN ,G : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(8 DOWNTO 1)); END ENTITY SN74373; ARCHITECTURE two OF SN74373 IS SIGNAL sigvec_save : STD_LOGIC_VECTOR(8 DOWNTO 1); BEGIN PROCESS(D, OEN, G , sigvec_save) BEGIN IF OEN = 0 THEN Q = sigvec_save; ELSE Q = ZZZZZZZZ; END IF; IF G = 1 THEN Sigvec_save = D; END IF; END PROCESS; END ARCHITECTURE two; ARCHITECTURE one OF SN74373 IS COMPONENT Latch PORT ( D, ENA : IN STD_LOGIC; Q : OUT STD_LOGIC ); END COMPONENT; SIGNAL sig_mid : STD_LOGIC_VECTOR( 8 DOWNTO 1 ); BEGIN GeLatch : FOR iNum IN 1 TO 8 GENERATE Latchx : Latch PORT MAP(D(iNum),G,sig_mid(iNum)); END GENERATE; Q = sig_mid WHEN OEN = 0 ELSE ZZZZZZZZ; --当OEN=1时，Q(8)~Q(1)输出状态呈高阻态 END ARCHITECTURE one; * KX康芯科技 【例10-28】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff IS PORT ( d, clk_s : IN STD_LOGIC ; q : OUT STD_LOGIC ; nq : OUT STD_LOGIC ); END ENTITY d_ff; ARCHITECTURE a_rs_ff OF d_ff IS BEGIN bin_p_rs_ff : PROCESS(CLK_S) BEGIN IF clk_s = 1 AND clk_sEVENT THEN q = d; nq = NOT d; END IF; END PROCESS; END ARCHITECTURE a_rs_ff; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY cnt_bin_n is GENERIC (n : INTEGER := 6); PORT (q : OUT STD_LOGIC_VECTOR (0 TO