10进位转BCD编码器.pptVIP

Figure 6--1 Logic symbol for a half-adder(半加器). Figure 6--2 Half-adder logic diagram. Figure 6--3 Logic symbol for a full-adder (全加器). Figure 6--4 Full-adder logic. Open file F06-04 to verify operation. Figure 6--5 Full-adder implemented with half-adders. 例題 6-1 求 圖 6-6 所示的三個全加器的輸出 Figure 6--7 Block diagram of a basic 2-bit parallel adder using two full-adders. Figure 6-8 根據公式計算一下答案！ Figure 6--9 A 4-bit parallel adder. 進位傳遞(carry propagation) 進位產生 進位傳遞 進位遞迴產生器 Figure A--2 Four-bit parallel adders. Figure A--3 Characteristics for the 74LS283. pp. A-3 四位元預見進位產生器 Figure 6--10 Examples of adder expansion. Figure 6--11 Two 74LS83A adders connected as an 8-bit parallel adder  (pin numbers are in parentheses). Figure 6--12 A voting system using full-adders and parallel binary adders. Figure 6--13 Basic comparator operation. Figure 6--14 Logic diagram for equality comparison of two 2-bit numbers.  Open file F06-16 to verify operation. Figure 6--15 Figure 6--16 Logic symbol for a 4-bit comparator with inequality indication. 例題 6-6 求 Figure 6—17 的輸出 Figure A--4 Pin diagram and logic symbol for the 74HC85 4-bit magnitude comparator (pin numbers are in parentheses). pp. A-4 Figure 6--19 An 8-bit magnitude comparator using two 74HC85s. Figure 6--20 Decoding logic for the binary code 1001 with an active-HIGH output. Figure 6--21 Decoding logic for producing a HIGH output when 1011 is on the inputs. Figure 6--22 Logic symbol for a 4-line-to-16-line (1-of-16) decoder.  Open file F06-24 to verify operation. Figure A—5a,b Pin diagram and logic symbol for the 74HC154 1-of-16 decoder. pp. A-5 Figure A—5c Pin diagram and logic symbol for the 74HC154 de-multiplexer. pp. A-5 Figure 6--23 A 5-bit decoder using 74HC154s. Figure 6--24 A simplified computer I/O port system with a port address decoder with only