基于门控时钟的片上网络路由单元低功耗设计-南京师范大学学报.pdfVIP

9 3 () Vo.l 9No. 3 2009 9 JOURNA OF NAN JING NORMA UN IVERSITY ( ENG INEERING AND TECHNO OGY EDIT ION ) Sep, 2009 基于门控时钟的片上网络路由单元低功耗设计 翟 亮, 吴 宁 ( , 210016) [] NoC( Netw ork-on-Chip), , NoC . NoC, M esh, , . M odelSmi SE P US 60, Synopsys Design Compiler , 200MHz, 510457mW, 1138% . [] , , , [ ] TP3021 [] A [] 1672-1292(2009) 03-0018-04 Low-Power Design of Router for NoC W ith Clock Gating Z ha i L iang, W u N ing ( College of Information T echnology Science, Nanjing University of Aeronautics and Astronautics, N anjing 210016, China) Abstract: Newt ork-on-Ch ip (NoC) arch itectures are gradually replacing interconnection on ch ip, and thusbecom ing an attractive solution to address the inter-connect delay problem s in System-on-Chip. However, increased pow er d issipation has h indered the w ide-dep loym ent ofNoCs. From Router, the kernelunit, on the basis of the study of the structure of router on the b i-dmi ensionalM esh ch ip and the techn ique of clock gating, the paper proposes a low-pow er design of Router w ith Model level Clock gating (M CG) techn iques, by using code to control the clock signal of the Input. Func- tional smi ulation is donew ithM odelSmi SE P US 60 tools. Resu lts of synthesisw ith design comp iler of the synopsys Inc. show that the dynam ic pow er consumption of a rou ter is reduced by 1138% w ith 200MHz operating frequency. K ey words: clock gating, NoC, ow-Pow er, rou ter NoC( Network-on-Chip) , N oC. , , . N oC, [ 1] NoC . NoC( Crossbar). , Crossbar [ 2] . , 4 4 NoC , , , . 1 路由单元结构与功耗分析 NoC, , . 1 , 5. : 2009-06-29. : ( BK2008387). : ,