DDS信号技术信号发生器设计.docVIP

基于DDS信号技术的信号发生器的设计 直接数字式频率合成技术DDS是新一代的频率合成技术，采用数字控制信号的相位增加技术，具有频率分辨率高，频率切换快，频率切换时相位连续和相位噪声低以及全数字化易于集成等优点而被广泛采用。 程序代码 ADDER32B library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ADDER32B is port( ain : in std_logic_vector(31 downto 0); bin : in std_logic_vector(31 downto 0); cout: ou t std_logic_vector(31 downto 0) ); end; architecture one of ADDER32B is begin cout = ain + bin; end; （2）juxing_rom LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY juxing_rom IS PORT ( address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END juxing_rom; ARCHITECTURE SYN OF juxing_rom IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( address_aclr_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q = sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_a = NONE, init_file = ../MIF/juxing.mif, intended_device_family = Cyclone, lpm_hint = ENABLE_RUNTIME_MOD=NO, lpm_type = altsyncram, numwords_a = 4096, operation_mode = ROM, outdata_aclr_a = NONE, outdata_reg_a = CLOCK0, widthad_a = 12, width_a = 8, width_byteena_a = 1 ) PORT MAP ( clock0 = clock, address_a = address, q_a = sub_wire0 ); END SYN; （3）mux3_1 library ieee; use ieee.std_logic_1164.all; entity mux3_1 is port( sin:in std_logic_vector(7 downto 0); sanjiao,juxing:in std_logic_vector(7 downto 0); a,b:in std_logic; cout:out std_logic_vector(7 downto 0) )