linux系统下ncverilog的详细命令linux系统下ncverilog的详细命令.doc

ncverilog: 08.10-p002: (c) Copyright 1995-2008 Cadence Design Systems, Inc. Usage: ncverilog [options] files File languages: Verilog, SystemVerilog, VHDL, e, System-C, C, C++ In addition to the dash options all ncverilog plus options can be used. Options shown below in lowercase can also be entered in uppercase. For example, both -top and -TOP are valid. If you need more information about an option listed below, use the search facility in the online help system. In the Search for text box, enter the name of the option, including the dash (-profile, for example). +access+/-rwc Turn on read, write and/or connectivity access +allow_unused_properties Allow simulator to enable all properties -allowredefinition Allow mutiple files to define the same object +amsconnrules+cellname specify connect rules to use +amsmatlab Dynamically link vpi code for AMS/Matlab -amsmt_enable to enable AMS multithread capability -amsmt_nthreads arg number of threads for AMS multithreading. -amsvhdl_ext ext Override extensions for VHDL AMS sources +append_key Append keystrokes to existing key file -arr_access Allow tf_nodeinfo access to Verilog arrays -asext ext Add extensions to assembly sources +assert Enable PSL language features +assert_count_traces Use trace-based counting for assertions +assert_sc Enable PSL language features +assert_vhdl Enable PSL language features +assert_vlog Enable PSL language features -bb_celldefine Blackbox all verilog modules within `celldefine -bb_nonsynth Blackbox unsynthesizable modules in halsynth -bb_unbound_comp Ignore unbounded component for synthesis checks -bb_vital Blackbox design-units containing VITAL constructs -c Parse and elaborate, do N