EDA考点缩印版1.docVIP

1、实验一：多路数据选择器（四选一） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41a IS PORT(a ,b ,c ,d : IN STD_LOGIC ; s1 ,s0 : IN STD_LOGIC ; y : OUT STD_LOGIC); END ENTITY mux41a; ARCHITECTURE one OF mux41a IS SIGNAL aa :STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN aa= s1 s0 ; PROCESS(aa) BEGIN CASE aa IS WHEN 00= y=a; WHEN 01= y=b; WHEN 10= y=c; WHEN 11= y=d; WHEN OTHERS= NULL; END CASE; END PROCESS; END ARCHITECTURE one; 2、实验二：8-3编码器 library ieee; use ieee.std_logic_1164.all; entity encoder is port(input:in std_logic_vector(7 downto 1); ein: in std_logic; output: out std_logic_vector(2 downto 0)); end entity; architecture aa of encoder is begin process(input,ein) begin if ein= 1 then output=111; elsif input(7)= 0 then out