笔误fpga随机断言随机比对定向比对定向测试代码检查占bug总量.ppt

The Verification of UniCore-II Microprocessor Sun Hanxin Peking University Microprocessor RD Center Outline Introduction to UniCore-II microprocessor Simulation-based verification methodology Bug driven activity Conclusions and future work Pkunity-3 Architecture UniCore-II Microprocessor UniCore Frequency: 600MHz 32-bit harvard-architecture RISC CPU UniCore32 instruction set compatible Add conditional mov BLX instructions 8-stage instruction pipeline Dynamic prediction policy: G-share Pipelined ID Cache Two-level TLB Design Verification Problem Functional verification is widely recognized as the bottleneck of hardware design cycle: The ever-growing demand for processor performance The dramatically increase in hardware complexity Low tolerance for bugs on finished product Time-to-market pressure Solution to Verification Problem Different Tests, Different Methods: Formal Verification: Small block test Simulation: Directed test Constrained-random test Simulation Acceleration: Regression test FPGA Prototyping: BIOS, Linux kernel, Application test Simulation-based Verification Simulation metric Checking scheme Test generation Simulation Metric Code coverage: line coverage toggle coverage FSM coverage condition coverage Functional coverage: pipelined instruction state coverage AHB bus transaction coverage Assertion coverage Checking Scheme Self-check assembly code OpenVera assertion Golden reference model comparison Checking Scheme SystemC in the design flow: Find out problems of documented specification Evaluate design early in the design cycle Golden reference model of RTL design verification Test Program Generation The key issue of processor verification: Test vector efficiency Verification time Quality of product Some examples of processor verification: Intel Pentium-4 verification Alpha21164 verification IBM Genesys, GenesysPro test generator Test Program Generation UniGener: UniCore-II test program generator Bug Driven Activity Bug Analysis: Exa