EDA_电子钟.docVIP

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity CDU24 is Port ( clk1 : in std_logic; clk2 : in std_logic; sa : in std_logic; mm : out std_logic_vector(7 downto 0); co : out std_logic); end CDU24; architecture Behavioral of CDU24 is signal count : std_logic_vector(7 downto 0); signal smm : std_logic_vector(7 downto 0); signal sco : std_logic; signal count2 : std_logic_vector(7 downto 0); signal smm2 : std_logic_vector(7 downto 0); signal sco2 : std_logic; signal flag : std_logic; begin process(clk1) begin if rising_edge(clk1) then --count=sco2+count; if flag=1 then count = count2; elsif count=then count = sco=1; else count = count+1; sco=0; end if; end if; if (9count and count20) then smm = count + 6; elsif (19count and count30) then smm = count + 12; else smm = count; end if; end process; process(clk2) begin if rising_edge(clk2) then if sa=1 then if count2 =then count2 = sco2=1; else count2 = count2+1; sco2=0; end if; flag=1; if (9count2 and count220) then mm = count2 + 6; elsif (19count2 and count230) then mm = count2 + 12; else mm = count2; end if; co =sco2; else if count=count2 then flag=0; end if; mm = smm; co =sco; end if; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEE