M74HC138RM13TR,M74HC138TTR,M74HC138B1R,规格书,Datasheet 资料精选.pdfVIP

M74HC138 3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: DIP SOP TSSOP |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL ORDER CODES WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T R VCC (OPR) = 2V to 6V DIP M74HC138B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC138M1R M74HC138RM13TR 74 SERIES 138 TSSOP M74HC138TTR DESCRIPTION The M74HC138 is an high speed CMOS 3 TO 8 inhibited and all the 8 outputs go high. Three LINE DECODER fabricated with silicon gate enable inputs are provided to ease cascade C2MOS technology. connection and application of address decoders If the device is enabled, 3 binary select inputs (A, for memory systems. B, and C) determine which one of the outputs will All inputs are equipped with protection circuits go low. If enable input G1 is held low or either G2A against static discharge and transient excess or G2B is held high, the decoding function is voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/10 芯天下--/ M74HC138 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION