浙江大学信电系数字系统设计II-A2012-试卷精选.pdfVIP

浙江大学2011 –2012 学年秋冬学期 《数字系统设计II》课程期末考试试卷 课程号：111C0130，开课学院：_信息与电子工程学系_ 考试试卷：√A 卷、B 卷（请在选定项上打√） 考试形式：√闭、开卷 （请在选定项上打√）， 允许带1 张A4 大小的手写资料和计算器入场 考试日期： 2012 年 1 月 15 日,考试时间： 120 分钟 诚信考试，沉着应考，杜绝违纪。 考生姓名： 学号： 所属院系（专业）： _ 题序 一 二 三 四 五 六 七 八 总 分 得分 评卷人 一、PEFORMANCE [10 分] Suppose that you have an un-pipelined process or which requires 10 clock cycles to perf orm a memory access, 4cycles to perform a branch, and 2 cycles to perform all other instructions. Suppose further that the processor clock frequency is 1500MHz. [4 分] 1.1. Suppose a program runs for 100billion dynamic instructions. The dynamic instructions consist of 30% memory accesses, 10% branches, and 60% other instructions. How much time will the program take to run? [3 分] 1.2. A new design technique allows you to run the processor at 2000MHz, but memory access now takes 15 cycles. How much faster would a processor using the new design technique be? [3 分] 1.3. Better compiler techniques might reduce the number of memory accesses. What is the highest speedup (relative to the original processor) possible by reducing the number of memory accesses if all other factors remain constant? 二、REGISTER FILE DESIGN [10分] The write logic for the register file design is shown in Figure1. Redesign the write logic for the register file, so that two registers may be written on the same positive clock edge. The 5-bit values ws1 and ws2 specify the registers to write, the 1-bit values WE1 and WE2 enable writing for each port (1 = enabled, 0 = disabled