射频关键性设计教程Lecture18_PA.ppt

Lecture 18 Richard Li, 2009 L = 7.3 nH L = 7.3 nH L = 7.3 nH L = 7.3 nH L = 7.3 nH Port 1 20 Ω Port 3 50 Ω Figure 33 Output balun built by inductors and capacitors f = 800 – 900 MHz, Balun: 2x20 Ω to 50 Ω, “Zero” capacitor: C =39 pF. L = 7.3 nH C = 7.5 pF MS SUB=RichardL H=25 mil. HU=1.0E+3 mil. mil. T=1 mil. ER = 10.5 MUR = 1 COND=1.0E+07 Rough = 0 μm TAND = 0.02 C = 7.5 pF C = 7.5 pF C = 7.5 pF C = 7.5pF C = 7.5 pF Port 2 20Ω Chip capacitor Ideal resistor Chip capacitor 50 Ω C = 39 pF C = 39 pF C = 39 pF Figure 34 S13 and S23 of output balun built by inductors and capacitors f = 800 – 900 MHz, Balun: 2x20 Ω to 50 Ω, “Zero” capacitor: C =39 pF. -1.0 0 S13, S23 dB -2.0 -3.0 -4.0 -5.0 800 820 840 860 Freq., MHz 880 S23 S13 900 900 -80 20 -20 -60 80 40 100 S13, S23 deg 60 0 -40 -100 800 820 840 860 880 S23 S13 Freq., MHz Figure 35 Evolution of balun applied to PA on a ceramic aluminate board. Thickness = 0.25 mil. εr = 10.5, μ r = 1, f = 800 – 900 MHz, In Out 3.15’’ 1.8’’ 1.38’’ λ/4 λ/4 λ/2 λ/4 λ/4 (a) Balun built by MSL only 1.15’’ 0.8’’ 2.00’’ Out In (b) Balun built by MSL and capacitors 0.92’’ 0.27’’ 0.9’’ Out In (c) Balun built by inductors and capacitors C=2.7 pF 4 DC blocking capacitors at upper and bottom corners: C = 39 pF At input balun L=6.6 nH, C=8.2 pF At output balun L=7.3 nH, C=7.5 pF 4 DC blocking capacitors at upper and bottom corners: C = 39 pF Micro strip line, Zo=35.4Ω, W=8 mils Chip resistor, 50 Ω Conductive hole Gold-plated copper Figure 36 Minimized layout of push-pull PA on a ceramic aluminate board. Thickness = 0.25 mil. εr = 10.5, μ r = 1, f = 800 – 900 MHz, Conductive hole Gold-plated copper Micro strip line, W=21 mil Gold-plated wire Vdd cable Bias cable SMA connector Chip resistor, 50 Ω RF choke, 0.2μH Device: CLY10, Siemens Chip capacitor, 4.12 pF Chip inducto