[工学]EDA基于FPGA的微波炉定时器芯片设计.ppt

微波炉定时器芯片的设计; 上电后，系统处于复位状态。; 5.微波管的驱动：设置一个输出驱动控制烹调状态的继电器即可。; 微波炉定时器芯片符号图; 微波炉定时器工作流程图; 微波炉定时器芯片的模块划分; MICRO-WARE; LOADER; 定时器模块: 其主要功能为计时和数据译码。Load有效时完成装入功能，down有效时执行减计数。 ; MICRO-WARE;1. 控制器的实现；控制器的状态图如图6.2.7 所示： ;控制器的VHDL描述如下：; architecture beh of microware is type state_type is (idle, l_test, c_set, timer, m_done); signal n_state, c_state: state_type; begin process(clk, reset) begin if reset = ’1’ then c_state = idle; elsif clk’event and clk=’1’ then c_state = n_state; end if; end process; process(c_state, set, start, test, done) begin n_state = idle; -- 缺省次态者为idle l_8888 = ‘0’; l_done = ‘0’; l_clk = ‘0’; cook = ‘0’; ; case c_state is when l_ test = l_8888 = ‘1’; when c_ set = l_clk = ‘1’; when m_ done = l_done = ‘1’; when idle = if test = ’1’ then n_state = l_ test; l_8888 = ‘1’; elsif set =’1’ then n_state = c_ set; l_clk = ‘1’; elsif (start =’1’) and (done = ‘0’) then n_state = timer; cook = ‘1’; end if; when timer = if done = ’1’ then n_state = m_ done; l_done = ‘1’; else n_state = timer; cook = ‘1’; end if; end case; end process; end beh;;2.装入器的实现： 装入器的功能类似于一个多路选择器，其完成的主要任务是把测试信息、时间设置信息和烹调结束信息送给定时和显示电路，下面是装入器的结构框图,其VHDL描述如下页所示。;装入器的VHDL描述如下：;architecture beh of loader is begin process(data, l_8888, l_clk, l_done) constant all_8:std_logic_vector(15 downto 0):= “1000100010001000”; constant done: std_logic_vector(15 downto 0):= “1010101111001101”; variable temp : std_logic_vector(2 downto 0 ); begin load = l_8888 or l_done or l_clk; temp := l_8888 l_done l_clk; case temp is when “100” = data_val = all_8; when “010” = data_val = done;