[信息与通信]vhdl实例.doc

2010-01-09 17:30 [例1.4.26] 2输入与门的VHDL描述LIBRARY IEEE;??? USE IEEE.STD_LOGIC_1164.ALL;ENTITY and2 IS PORT(a, b : IN STD_LOGIC; ?????????? y: OUT STD_LOGIC); END and2; ARCHITECTURE one OF and2 ISBEGIN???? y= a and b;END one; [例2.5.2] 2输入或门的VHDL描述LIBRARY IEEE;??? USE IEEE.STD_LOGIC_1164.ALL;ENTITY or2 IS PORT(a, b : IN STD_LOGIC; ?????????? y: OUT STD_LOGIC); END or2; ARCHITECTURE one OF or2 ISBEGIN???? y= a or b;END one; [例2.5.3]非门的VHDL描述LIBRARY IEEE;??? USE IEEE.STD_LOGIC_1164.ALL;ENTITY hnot IS PORT(a : IN STD_LOGIC; ?????????? y: OUT STD_LOGIC); END hnot; ARCHIT