laker使用教程.ppt

IC Layout Tool Laker Candace SSCAS Pin-Dai Sue Outline Laker Base Operate ………………………………………………….P3 Candace Base Operate ……………………………………..……….P11 Virtuoso Base Operate …………………..…………………………..P14 DRC Check……………………………………………………..……..P18 LVS Check………………………………………………….…..……..P22 PEX………………………………………………………….…..……..P27 Matching…………………………………………………………….…P31 Laker – Create New Library Library → New… Laker – Create New Cell Cell → New… Laker – Tool Interface Laker – Layer Level Laker – Create Contact Create → Contact… Hot key: o Laker - Create Transistor Create → Transistor… Hot key: Ctrl + m Laker – Example PMOS PMOS　　 Laker – Example NMOS NMOS　　 Laker – Example Inverter Inverter Layout Candace – Open Library Manager Tools → Library Manager… Candace – Create New Library File → New →Library… Candace – Create New Cell (Schematic) File → New → Cell View… Schematic – Tool Interface Schematic – Create Component (1/2) Schematic – Create Component (2/2) Schematic – Example Inverter DRC Check – Open DRC Check layout layer rule DRC Check – Define DRC Rule DRC Check – Define DRC Rule DRC Check – Highlight Error LVS Check – Open LVS Against with layout and schematic LVS Check – Define LVS Rule LVS Check – Define Netlist File LVS Check – NO Error LVS Check – Error PEX – Open PEX PEX - Define PEX Rule PEX – Define Netlist File PEX – PEX Result Matching – Resistor Matching Matching – Capacitor Matching Matching – MOS Matching (1/3) Matching – MOS Matching (2/3) Matching – MOS Matching (3/3) R1 R2 80k 80k R1 R2 R1 R2 R1 R2 20k 80k R1 R2 R1 R2 40K 40K 40K 40K 40k+40k 40k+40k 40k+40k 40k // 40k C1=0.2p C2=0.2p C1 C2 C2 C1 0.1p 0.1p 0.1p 0.1p C1=0.8p C2=0.1p C1 C1 C1 C1 C2 C1 C1 C1 C1 0.1p // 0.1p 0.1p // 0.1p 80m/1m G S D B G S D G S D G S D G S D 20m G S D G S D G G S 20m * P.D Sue SSCAS * Define Library Name Chose Technology File Chose Library Defined Cell Name Layer Table Create Rectangle Hot key: r Create Polygon Hot key: Shift + p Create Path Hot key: p Create text H