数字电路EDA设计(第二版)第六章_典型数字系统设计教材教学课件.pptVIP

第六章 典型数字系统设计 ;分频电路;偶数分频 ;ARCHITECTURE a OF div_fre IS SIGNAL cnt: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL div_tmp:STD_LOGIC; BEGIN PROCESS (clk) BEGIN IF (rst=1) THEN cnt=0000; ELSIF (clk’EVENT AND clk=1) THEN IF (cnt=1111) THEN cnt= (OTHERS=0); div_tmp=1; ELSE cnt=cnt+1; div_tmp=0; END IF; END IF; END PROCESS; div_out=div_tmp; END a;;奇数分频 ;ARCHITECTURE a OF div_fre IS SIGNAL cnt: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL div_tmp:STD_LOGIC; BEGIN PROCESS (clk) BEGIN IF (rst=1) THEN cnt=0000; ELSIF (clk’EVENT AND clk=1) THEN IF (cnt=1110) THEN div_tmp=NOT div_tmp; cnt= (OTHERS=0); ELSIF (cnt=0111) THEN div_tmp=NOT div_tmp; cnt= cnt+1; ELSE cnt=cnt+1; END IF; END IF; END PROCESS; div_out=div_tmp; END a;;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY div_fre IS PORT (clk：IN STD_LOGIC; rst：IN STD_LOGIC; div_out：OUT STD_LOGIC); END div_fre; ARCHITECTURE a OF div_fre IS SIGNAL cnt1,cnt2: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL div_tmp1,div_tmp2:STD_LOGIC; BEGIN PROCESS (clk,rst) BEGIN IF (rst=1) THEN cnt1=0000; ELSIF (clk’EVENT AND clk=1) THEN IF (cnt1=1110) THEN div_tmp1=NOT div_tmp1; cnt1= (OTHERS=0); ELSIF (cnt1=0111) THEN div_tmp1=NOT div_tmp1; cnt1= cnt1+1; ELSE cnt1=cnt1+1; END IF; END IF; END PROCESS; PROCESS(clk,rst) BEGIN IF (rst=1) THEN cnt2=0000; ELSIF (CLK’EVENT AND CLK=0) THEN IF (cnt2=1110) THEN div_tmp2=NOT div_tmp2; cnt2= (OTHERS=0); ELSIF (cnt2=0111) THEN div_tmp2=NOT div_tmp2; cnt2= cnt2+1; ELSE cnt2=cnt2+1; END IF; END IF; END PROCESS; div_out=div_tmp1 OR div_tmp2; END a;; X.5分频 ;分频器的硬件验证 ;交通灯控制器;交通控制灯的功能描述 ; 交通灯控制器的实现;; 交通控制灯的VHDL程序 ;交通控制灯的硬件验证 ;数字频率计 ;频率计的组成结构分析 ;1．测频控制信号发生器：频率计设计的关键是设计一个测频控制信号发生器，产生测量频率的控制时序。控制时钟信号clk取为1Hz，二分频后即可产生一个脉宽为1s的时钟test_en，以此作为计数闸门信号。当test_en为