官方说明书ST 74V2T132 数据手册.pdfVIP

ST 74V2T132 handbook /file/2714071 From ManualL ManualL collects and classifies the global product instrunction manuals to help users access anytime and anywhere, helping users make better use of products. Home: / Chinese: / This Manual: /file/2714071 查询74V2T132 供应商 74V2T132 DUAL 2-INPUT SHMITT TRIGGER NAND GATE HIGH SPEED: tPD = 3.7 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 1 µA (MAX.) at TA = 25°C TYPICAL HYSTERESIS: 0.8V at VCC = 4.5V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: SOT23-8L tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V ORDER CODES IMPROVED LATCH-UP IMMUNITY PACKAGE T R SOT23-8L 74V2T132STR DESCRIPTION The 74V2T132 is an advanced high-speed CMOS The internal circuit is composed of 3 stages SINGLE 2-INPUT NAND GATE fabricated with including buffer output, which provide high noise sub-micron silicon gate and double-layer metal immunity and stable output. wiring C2MOS technology. Power down protection is provided on all inputs Pin configuration and function are the same as and 0 to 7V can be accepted on inputs with no those of the 74V2T00 but the 74V2T132 has regard to the supply voltage.