双语课件（第8章） 8. Motivation for HDL 《数字的设计基础（双语教学版）》Barry Wilknson .pptVIP

* 8. Motivation for HDL 8.1 Problems with low level methods 8.2 Hardware Description Languages 8.3 Behavioral and structural description 8.4 Synthesis and Simulation 8.1 Problems with low level methods Low level methods of logic design require the designer to get heavily involved in what each logic gate and flip-flop must do. 1. low level methods 2. higher level methods Higher level methods aim to free the designer from the detail by automating the low level tasks and to enable them to concentrate on the overall architecture of a digital system. 8.2 Hardware Description Languages 1. Two important HDLs: VHDL and Verilog Exp1: Describe a comparator in two HDLs. VHDL: g = ’1’ when ab else ’0’; Verilog: assign g = ab ? 1 : 0; VHDL is the VHSIC Hardware Description Language. VHSIC stands for Very High Speed Integrated Circuit. 8.2 Hardware Description Languages To provide a language for rigorous and unambiguous specification of modules. Gradually it developed to be used for other purposes such as synthesis. 2. Main motivation for VHDL 8.3 Behavioral and structural description Structural descriptions tell us how we would make it but not what it would do. 3. Structural descriptions It tells us how we would connect together several simpler units to make a more complicated unit. 8.3 Behavioral and structural description Structural description, showing how 1-bit adders connect together to form a 4-bit adder 8.3 Behavioral and structural description The description consists the interconnection of basic building blocks that are available to implement the design. A netlist contains sufficient detail that it is immediately obvious how to build the device. Netlist 8.4 Synthesis and Simulation 1. logic synthesis The process that turns the behavioral description into a netlist is called logic synthesis. 2. logic simulation The process that imagines the different inputs taking different values, and tracking the effects of the different