飞思卡尔后背资料2.pptVIP

Resets  Interrupts External InternalResets Crystal Loss/Stop Reset Recovery Sequence Interrupt Sources Interrupt Vector Table (2 of 3) Interrupt Vector Table (3 of 3) Interrupt Priority Control Real-Time Interrupt Real-Time Control/Status Registers S12 Oscillator Layout HCS12 Technical Training Module 5 – Resets Interrupts, Slide * MOTOROLA and the Stylized M Logo are registered in the US Patent Trademark Office. All other product or service names are the property of their respective owners. ? Motorola, Inc. 2001. ? Power-On Reset ? External Hardware Reset ? Crystal Monitor ? Computer Operating Properly Real time interrupt Power On Reset ? Initiated by positive transition on VDD. 8192 E clock delay is built in to allow oscillator to stabilize. VDD CPU CLK DATA BUS/ ADDRESS BUS IRESET 8192 ECLK Cycles Internal Reset is held low by MCU For about 8192 E clocks ? In General: Subsystems and control bits are initialized to have least effect on system ( I.e. interrupts masked, ports read only, serial communication disabled,...) V F P P P V - VECTOR FETCH F - FREE CYCLE P - PROGRAM FETCH FFFE FFFE 1st Opcode 2nd Opcode 3rd Opcode 128 ECLK Cycles 64 ECLK Cycles ? RESET pin asserted for 2 E clocks. ? RESET pin must negate before reset service can begin. ? No delay to stabilize oscillator. 64 ECLK CYCLES 32 ECLK CYCLES CPU CLK DATA BUS/ ADDRESS BUS RESET IRESET 96 E Clocks SAMPLE PIN FFFE FFFE 1st Opcode 2nd Opcode 3nd Opcode Crystal Monitor (1 of 2) Useful for: 1. Automatic Reset from a slow or stopped clock. 2. Improves fault tolerance of system. Description: If the E clock drops below a frequency of 10 KHZ* and the Crystal Monitor function has been enabled, then: 1. system reset is asserted on the external reset pin. 2. Crystal