强激光布里渊增强四波混频 相位共轭技术研究 - Retroconferences.pptVIP

* An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications Guohe Yin, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang Macau University * * 1. Introduction to SAR ADC 2. Proposed ADC Architecture 3. Circuit Implementation 4. Simulation Results 5. Conclusions Outline * * 1.The SAR ADC * 10 bit charge redistribution SAR ADC Advantages: Low power; Simple architecture; Middle area; Disadvantages: The capacitor ratio increase extremely with the resolution. So, for the 10-bit ADC, the MSB capacitor is 512C!! * 2. Proposed ADC Architecture * The proposed 9-bit two-stage pipelined ADC architecture * * Timing diagram of pipelined SAR ADC 2. Proposed ADC Architecture * 3. Switch scheme * Capacitive DAC arrays of the 10-bit pipelined SAR ADC Advantages: MSB capacitor 16C, not 512C; No op-amp; * * Circuit diagram of MSB and LSB DAC arrays in sharing phase 3. Switch scheme Not Vcm!! * * The output voltage of the DAC array: After sharing phase, LSB-array voltage: Before sharing phase, MSB-array voltage: 3. Switch scheme * * MSB and LSB DAC arrays in sharing phase with determined LSB reference voltage 3. Switch scheme * 4. Circuit Implementation * The Dynamic latch with Pre-amplifier gain 16. 4.1 The comparator * * 4.2 Digital Error Correction To eliminate the offset of two comparators, the last bit of coarse and the first bit of the fine stage are combined into one bit for overlapping. 4.3 Successive Approximation Register (SAR) In this ADC, only 6-DFFs instead of 11 in SAR ADC, low digital power. 4.4 Reference Ladder Resistor/tap = 1.6 K Ohm Unit capacitance =16 fF for the DAC Array 4. Circuit Implementation * 5. Simulation Result * Fig.9 Simulated DNL and INL The static performance DNL (differential nonlinearity) : +0.46/-0.66 LSB INL (integral nonlinearity) : +0.37/-0.53 LSB * 5. Simulation Result * Fig.13. Simulated SNDR versus sampling rate. Fig.12. Simulated SNDR versus input frequen