For Spatially Partitioned Processors Motivation空间分区的处理器的动机.pptVIP

Register Allocation for EDGE ISAs Block atomic execution Instruction groups fetch, execute, and commit atomically Direct instruction communication Explicitly encode dataflow graph by specifying targets EEMBC Results 1.33,1.39 Average 5% improvement EEMBC Results 1.33,1.39 Average 5% improvement EEMBC Results 1.33,1.39 Average 5% improvement Sample Spatial Allocations Separate memory traffic st + v0 v1 v2 v0 v2 v1 v0 v1 v2 + st + fbital HCSB Spatial st SPEC Results 1.22,1.22,1.23 Average 5% improvement SPEC Results 1.22,1.22,1.23 Average 5% improvement Conclusions Spatial locality among registers matters Register dependence graph can help Avoids spilling critical registers Flexible tool to incorporate locality information Modeling the topology is important Non-uniform distribution of registers/L1 cache banks Separate different types of traffic EDGE ISA eases burden on register allocator Spills are rare Spatial locality and contention become first-order constraints Questions? Today I will be talking how our traditional register allocation algorithms change when processors become spatially partitioned at a fine granularity Register files, reservation stations, memory banks, issue queues all partitioned among processing elements Wire delay, frequency scaling, power Locations are spatially distributed, and 2. Contention The 3/3 between B0 and E0 could just as easily be 2/4, if the scheduler didn’t know what it was doing. Make sure it is clear that this is a real chip. Make sure it is clear verbally that an instruction can be placed in any location Emphasize that we do static instruction placement, thus the compiler is responsible for placing instructions. Highlight the stage where the compiler does its thing and register allocation happens. * The first arrow is bigger because that really is an iterative process. We always iterate. The second arrow is dotted and smaller because we only sometimes iterate - only if we spill, and spilling causes a block to exceed its