BOUNDARY SCAN - Departamento de Electricidad y Electrónica边界扫描电子与电力部门与公司# 243.ppt

BOUNDARY SCAN - Departamento de Electricidad y Electrónica边界扫描电子与电力部门与公司# 243.ppt

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BOUNDARYSCAN-DepartamentodeElectricidadyElectr

BOUNDARY SCAN IEEE 1149.1 JTAG Boundary Scan Standard Motivation Bed-of-nails tester System view of boundary scan hardware Elementary scan cell Test Access Port (TAP) controller Boundary scan instructions Motivation for Standard Bed-of-Nails Tester Concept Purpose of Standard System Test Logic Instruction Register Loading with JTAG System View of Interconnect Boundary Scan Chain View Elementary Boundary Scan Cell Serial Board / MCM Scan Parallel Board / MCM Scan Independent Path Board / MCM Scan Tap Controller Signals Tap Controller State Diagram Tap Controller Timing TAP Controller Power-Up Reset Logic Boundary Scan Instructions SAMPLE / PRELOAD Instruction -- SAMPLE SAMPLE / PRELOAD Instruction -- PRELOAD EXTEST Instruction INTEST Instruction INTEST Instruction Clocks RUNBIST Instruction CLAMP Instruction IDCODE Instruction Device ID Register --JEDEC Code 31 28 Version (4 bits) USERCODE Instruction Purpose: Intended for user-programmable components (FPGA’s, EEPROMs, etc.) Allows external tester to determine user programming of component Selects the device identification register as serially connected between TDI and TDO User-programmable ID code loaded into device identification register On rising TCK edge Switches component test hardware to its system function Required when Device ID register included on user-programmable component HIGHZ Instruction BYPASS Instruction Optional / Required Instructions Dise?o ASIC BOUNDARY SCAN Dise?o ASIC BOUNDARY SCAN Bed-of-nails printed circuit board tester gone We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance Nails would hit components Reduced spacing between PCB wires Nails would short the wires PCB Tester must be replaced with built-in test delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors Test bus identical for various components One chip has test hardware for other chips Lets test ins

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